Differential circuits are circuits that provide and detect a voltage difference between two conductive lines. Differential circuits are ideally immune to small amounts of common mode noise. Nonetheless, such circuits may fail if a sufficient amount of common mode noise is present. Common mode noise is a disturbance that affects a plurality of lines similarly (e.g., causing a change of voltage of similar polarity and amplitude on each of the lines).
Common mode noise may be induced upon differential lines by another line that is parasitically coupled to the differential lines. The lines may be conductors, for example conductors formed in a metal layer of an integrated circuit or wires. The lines may carry signals. The signals carried by the line that is parasitically coupled to the differential lines may affect the signals carried by the differential lines through the effect of the parasitic coupling.
For example, if a line is in close proximity to the differential lines, a parasitic capacitance may exist between the line and each of the differential lines (referred to here as a parasitic capacitor). A current may flow through the parasitic capacitors and alter the amount of charge on the differential lines.
Since I=C dV/dt, the amount of current flowing through the parasitic capacitors is proportional to the capacitance of the parasitic capacitors and to the rate of voltage change on the line that is influencing the differential lines. Thus, signals that change voltage quickly, such as digital signals, can induce large amounts of common mode current noise on differential lines. If the source of the differential signal has a large output impedance, then current noise translates into voltage noise according to the relationship V=IR. Since digital signals are prevalent in modern electronic circuits, the introduction of common mode noise on differential lines is difficult to avoid.
While differential circuits are often designed to have a high common mode rejection ratio and thereby reject common mode noise, other effects can result in common mode noise being converted to differential mode noise. Differential mode noise is a disturbance that affects a plurality of lines dissimilarly (e.g., causing a change of voltage of opposite polarity and/or different amplitude on each of the lines). Differential mode noise can affect a differential circuit much more adversely than common mode noise. Parasitic diodes between a signal line and positive or negative voltage supplies often result from practical semiconductor fabrication techniques. Also, diodes may be intentionally introduced between a signal line and positive or negative voltage supplies to improve immunity to electrostatic discharge effects.
When the amplitude of common mode noise introduced on a differential pair causes the voltage on either or both of the differential lines to exceed the thresholds at which the parasitic diodes begin to conduct, current flows through the parasitic diodes, causing charge to be added to or removed from the differential lines in unequal amounts. Differential mode noise results from this unequal change in charge on the differential lines. Thus, the parasitic diodes can effectively convert common mode noise to differential mode noise. If the parasitic diodes of both differential lines begin to conduct, the signal carried by the differential lines may be completely lost, preventing proper operation of the differential circuit.
FIG. 1 is a schematic diagram illustrating a differential circuit affected by parasitic elements. The differential circuit comprises high impedance source 101, differential sense circuit 102, differential line 103, differential line 104, and output 105. High impedance source 101 may be a memory cell or another source. The differential circuit also comprises parasitic elements 106, which are usually unwanted and unavoidable, but commonly result from practical semiconductor fabrication techniques. Parasitic elements 106 comprise parasitic capacitors 108, 109, 111, and 112, and parasitic diodes 115, 116, 117, and 118.
High impedance source 101 provides a differential output signal at the pair of differential lines that comprises differential line 103 and differential line 104. Differential lines 103 and 104 are coupled to inputs of differential sense circuit 102. Differential sense circuit 102 provides an output signal at output 105.
Line 107 passes near or across differential lines 103 and 104 and induces voltage changes on differential lines 103 and 104. Line 107 induces a voltage changes on differential line 103 via parasitic capacitor 108 and on differential line 104 via parasitic capacitor 109. Line 107 is coupled to a first terminal of parasitic capacitor 108 and to a first terminal of parasitic capacitor 109. A second terminal of parasitic capacitor 108 is coupled to differential line 103. A second terminal of parasitic capacitor 109 is coupled to differential line 104.
A first terminal of each of parasitic capacitors 111 and 112 is coupled to ground potential 110. A second terminal of parasitic capacitor 111 is coupled to differential line 103. A second terminal of parasitic capacitor 112 is coupled to differential line 104. Parasitic capacitors such as parasitic capacitor 111 and 112 between differential lines and a ground potential often result from proximity of the differential lines to ground potentials, such as a ground plane, or to DC voltage supplies or other conductors at DC voltages.
Parasitic diodes also exist between differential lines and positive (e.g., V.sub.DD) and negative (e.g., ground) voltage supplies. The cathode of parasitic diode 115 is coupled to positive voltage supply 113. The anode of parasitic diode 115 is coupled to differential line 103. The cathode of parasitic diode 116 is coupled to differential line 103. The anode of parasitic diode 116 is coupled to negative voltage supply 114, which may be a ground potential. The cathode of parasitic diode 117 is coupled to positive voltage supply 113. The anode of parasitic diode 117 is coupled to differential line 104. The cathode of parasitic diode 118 is coupled to differential line 104. The anode of parasitic diode 118 is coupled to negative voltage supply 114.
FIGS. 2a and 2b are diagrams illustrating an effect whereby parasitic diodes 115, 116, 117, and 118 can cause common mode noise induced on differential lines 103 and 104 by line 107 to result in differential mode noise on differential lines 103 and 104. FIG. 2a illustrates a possible effect of a positive-going transition of the signal on line 107. FIG. 2b illustrates a possible effect of a negative-going transition of the signal on line 107.
Waveform 201 represents voltage x at differential line 103. Waveform 202 represents voltage x at differential line 104. Waveform 203 represents voltage y at line 107. Waveforms 201, 202, and 203 are shown relative to zero voltage level 204 representative of negative voltage supply 114, V.sub.DD voltage level 205 representative of positive voltage supply 113, and V.sub.DD +V.sub.TDP voltage level 206 representative of positive voltage supply 113 plus the forward voltage of parasitic diodes 115 and 117.
Waveforms 201, 202, and 203 are shown with time increasing from left to right. Waveforms 201 and 202 begin somewhat below V.sub.DD voltage level 205. Waveform 201 increases in voltage over time, while waveform 202 decreases in voltage over time. The divergence of waveforms 201 and 202 represents an increasing differential mode signal being provided by high impedance source 101.
At time 207, waveform 203 begins its transition from zero voltage level 204 to V.sub.DD voltage level 205. As waveform 203 begins to increase in voltage, its voltage change induces a voltage change in waveforms 201 and 202 through the effect of parasitic capacitors 108 and 109. The induced voltage on differential line 103 causes waveform 201 to continue to rise until it reaches V.sub.DD +V.sub.TDP voltage level 206 at time 208, at which point parasitic diode 115 begins to conduct and to clamp the voltage on differential line 103 at V.sub.DD +V.sub.TDP voltage level 206.
The induced voltage on differential line 104 causes waveform 202 to continue to rise until it reaches V.sub.DD +V.sub.TDP voltage level 206 at time 209, at which point parasitic diode 117 begins to conduct and to clamp the voltage on differential line 104 at V.sub.DD +V.sub.TDP voltage level 206. After waveform 203 completes its transition to V.sub.DD voltage level 205 at time 210, line 107 no longer induces a voltage on differential lines 103 and 104, and waveforms 201 and 202 again begin to diverge under the influence of the output of high impedance source 101.
Beginning at time 207, the influence of waveform 203 on waveforms 201 and 202 causes common mode noise to be induced upon waveforms 201 and 202. When the parasitic diodes begin to conduct at time 208, the continuing influence of waveform 203 begins to be converted from common mode noise to differential mode noise. At time 209, when parasitic diodes are clamping both differential lines 103 and 104, the continuing influence of waveform 203 in combination with the clamping effect of the parasitic diodes results in complete suppression of the differential signal across differential lines 103 and 104.
A similar situation occurs when voltage y on line 107 makes a negative-going transition. Waveform 211 represents voltage x at differential line 103. Waveform 212 represents voltage x at differential line 104. Waveform 213 represents voltage y at line 107. Waveforms 211, 212, and 213 are shown relative to zero voltage level 214 representative of negative voltage supply 114, V.sub.DD voltage level 215 representative of positive voltage supply 113, and -V.sub.TDN voltage level 216 representative of negative voltage supply 114 minus the forward voltage of parasitic diodes 116 and 118.
Waveforms 211, 212, and 213 are shown with time increasing from left to right. Waveforms 211 and 212 begin somewhat above zero voltage level 214. Waveform 211 increases in voltage over time, while waveform 212 decreases in voltage over time. The divergence of waveforms 211 and 212 represents an increasing differential mode signal being provided by high impedance source 101.
At time 217, waveform 213 begins its transition from V.sub.DD voltage level 215 to zero voltage level 214. As waveform 213 begins to decrease in voltage, its voltage change induces a voltage change in waveforms 211 and 212 through the effect of parasitic capacitors 108 and 109. The induced voltage on differential line 104 causes waveform 212 to continue to fall until it reaches -V.sub.TDN voltage level 216 at time 218, at which point parasitic diode 118 begins to conduct and to clamp the voltage on differential line 104 at -V.sub.TDN voltage level 216.
The induced voltage on differential line 103 causes waveform 211 to continue to fall until it reaches -V.sub.TDN voltage level 216 at time 219, at which point parasitic diode 116 begins to conduct and to clamp the voltage on differential line 103 at -V.sub.TDN voltage level 216. After waveform 213 completes its transition to zero voltage level 214 at time 220, line 107 no longer induces a voltage on differential lines 103 and 104, and waveforms 211 and 212 again begin to diverge under the influence of the output of high impedance source 101.
Beginning at time 217, the influence of waveform 213 on waveforms 211 and 212 causes common mode noise to be induced upon waveforms 211 and 212. When the parasitic diodes begin to conduct at time 218, the continuing influence of waveform 213 begins to be converted from common mode noise to differential mode noise. At time 219, when parasitic diodes are clamping both differential lines 103 and 104, the continuing influence of waveform 213 in combination with the clamping effect of the parasitic diodes results in complete suppression of the differential signal across differential lines 103 and 104.
Thus, the need for a technique to improve immunity to common mode noise resulting from voltage changes on line 107 can be readily appreciated.
In the past, such common mode noise problems have been addressed by attempting to make the ratio of C.sub.y to C.sub.g as small as possible. However, there is a finite limit to how small C.sub.y can be in a practical implementation. Thus, to make the ratio of C.sub.y to C.sub.g small, C.sub.g has to be larger than its smallest practical value. The larger C.sub.g is, the more it adversely affects the performance of the circuit. While a large C.sub.g results in reduced common mode noise , it also increases the sensing time required by the differential sense circuit, slowing down the operation of the circuit.
Another approach that has been used to reduce common mode noise is to limit the number of lines that are allowed to carry signals that switch in a manner that might induce common mode noise on the differential lines. However, such a limitation introduces an additional constraint that can also reduce performance of the circuit. Moreover, such an approach does not actually fortify the differential lines against common mode noise, but attempts to avoid signals that might cause common mode noise. The differential lines remain sensitive to the effects of common mode noise and may be adversely affected by other sources of common mode noise.
Thus, a better technique for improving immunity to common mode noise is needed.